摘要:
ADF4193频率合成器可用于实现本机振荡在上变频和下变频部分的无线电接收机和发射机。对基站而言,它的设计目的是为满足GSM/EDGE的松簧时间。它由一低噪声、数字相频检波器（PFD）和一精密充电泵组成。对外部压控振荡器（VCO）来说，还有一差分放大器转换为差动充电泵输出单一终端电压。对N分频器而言，Σ-Δ装置的部分插入器允许可编程模数部分的N分频。另外，４位基准（R）计数器和芯片内倍频器允许基准信号（REFIN）频率在PFD的输入。如果合成器被用于外部环路滤波器和一压控振荡器,可用一完全相位锁定环路（PLL）。交换结构确保了锁相环调整内部时间间隙在保护期间，消除了对一次锁相环和隔离开关的需要。这种设计降低了成本、复杂性、保护电路和特性在开关式GSM PLL结构中。
Abstract：
The ADF4193 frequency synthesizer can be used to implement local oscillators in the up conversion and down conversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single ended voltage for the external voltage controlled oscillator (VCO). The Σ-Δ based fractional interpolator, working with the N divider, allow programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency douber allows selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures .
